v810 Instruction Summary

V810 Opcode Formats:

Form 1 (I) - Register to Register computation, 16-bit
0F0E0D0C0B0A09080706050403020100
opcode reg2 reg1

Form 2 (II) - Immediate to Register computation, 16-bit
0F0E0D0C0B0A09080706050403020100
opcode reg2 Imm5

Form 3 (III) - Conditional Branch, 16-bit instruction
0F0E0D0C0B0A09080706050403020100
opcode disp9 0

Form 4 (IV) - Medium Jump, 32-bit
0F0E0D0C0B0A09080706050403020100
opcode disp26
1F1E1D1C1B1A19181716151413121110
disp26 (continued)

Form 5 (V) - 3 operand instruction, 32-bit
0F0E0D0C0B0A09080706050403020100
opcode reg2 reg1
1F1E1D1C1B1A19181716151413121110
imm16

Form 6 (VIa/b) - load/store instruction, 32-bit
0F0E0D0C0B0A09080706050403020100
opcode reg2 reg1
1F1E1D1C1B1A19181716151413121110
disp16

Form 7 (VII) - extended instruction, 32-bit (floating point/bitstring)
0F0E0D0C0B0A09080706050403020100
opcode reg2 reg1
1F1E1D1C1B1A19181716151413121110
sub-opcode RFU

RFU
Reserved for Future Use
reg1,2
5-bit int referencing general purpose registers 0 to 31.
imm5
5-bit immediate data, sign extended to 32-bit.
Disp9
9-bit displacement, sign extended to 32-bit.
imm16
16-bit Immediate data, sign extended to 32-bit.
disp16
16-bit displacement, sign extended to 32-bit.
disp26
26-bit displacement, sign extended to 32-bit.
SReg
5-bit int referencing system registers 0 to 31.
vector
5-bit address of, trap vector 0-31. 
opcode	form	instruction	summary
-------------------------------------
--Register to Register computation--------------
0x00	I	mov reg1, reg2	Move			reg2 <-- reg1
0x01	I	add reg1, reg2	Add			reg2 <-- reg2 + reg1
0x02	I	sub reg1, reg2	Subtract		reg2 <-- reg2 - reg1
0x03	I	cmp reg1, reg2	Comparison		reg2 - reg1
0x04	I	shl reg1, reg2	Logical shift left
0x05	I	shr reg1, reg2	Logical shift right
0x06	I	jmp [reg1]	Uncond. Branch		PC <-- reg1
0x07	I	sar reg1, reg2	Arithmetic shift right
0x08	I	mul reg1, reg2	Signed mult		r30,reg2 <-- reg2 * reg1
0x09	I	div reg1, reg2	Signed division		reg2 <-- reg2 / reg1
0x0A	I	mulu reg1, reg2	Unsigned mult		r30,reg2 <-- reg2 * reg1
0x0B	I	divu reg1, reg2	Unsigned division	reg2 <-- reg2 / reg1
0x0C	I	or reg1, reg2	Logical OR		reg2 <-- reg2 OR reg1
0x0D	I	and reg1, reg2	Logical AND		reg2 <-- reg2 AND reg1
0x0E	I	xor reg1, reg2	Logical XOR		reg2 <-- reg2 XOR reg1
0x0F	I	not reg1, reg2	Logical NOT		reg2 <-- NOT reg1

--Immediate to Register computation-------------
0x10	II	mov imm5, reg2	Move			reg2 <-- sign32(imm5)
0x11	II	add imm5, reg2	Add			reg2 <-- reg2 + sign32(imm5)
0x12	II	setf imm5, reg2	Test flag condition
0x13	II	cmp imm5, reg2	Comparison		reg2 - sign32(imm5)
0x14	II	shl imm5, reg2	Logical shift left	reg2 <-- reg2 << imm5
0x15	II	shr imm5, reg2	Logical shift right	reg2 <-- reg2 >> imm5
0x16	II	EI		v830?
0x17	II	sar imm5, reg2	Arithmetic shift right
0x18	II	trap vector	Software trap; imm5 is the vector
0x19	II	reti		Return from Int; no reg2 or imm5 data
0x1A	II	halt		Halt Processor; no reg2 or imm5 data
0x1B	UDEF			Undefined
0x1C	II	ldsr reg2, SReg	Load system register	SReg <-- reg2
0x1D	II	stsr SReg, reg2	Store system register	reg2 <-- SReg
0x1E	II	DI		v830?
0x1F	II	BitString Instructions; imm5 is sub-opcode
		See sub-opcode table below


--Conditional Branch, form 3 uses 7-bit opcode--
All follow the form: PC <-- PC + sign32(dsp9) depending on the flags
0x40	III	bv disp9	if Overflow 			[OV = 1]
0x41	III	bl disp9	if Lower (<; Unsigned)		[CY = 1]
				also BC: if Carry
0x42	III	be disp9	if Equal			[Z = 1]
				also BZ: if Zero
0x43	III	bnh disp9	if Not higher (<=; unsigned)	[(CY or Z) = 1]
0x44	III	bn disp9	if Negative			[S = 1]
0x45	III	br disp9	Always (unconditional branch)
0x46	III	blt disp9	if Less than; signed		[(SX xor OV) = 1]
0x47	III	ble disp9	if Less than or equal; signed	[((SX xor OV) or Z) = 1]
0x48	III	bnv disp9	if Not overflow			[OV = 0]
0x49	III	bnl disp9	if Not lower (>=; unsigned)	[CY = 0]
				also BNC: if Not carry
0x4A	III	bne disp9	if Not Equal			[Z = 0]
				also BNZ: if Not zero
0x4B	III	bh disp9	if Higher (>; unsigned)	[(CY or Z) = 0]
0x4C	III	bp disp9	if Positive			[S = 0]
0x4D	III	nop disp9	No Operation (do nothing for 1 cycle)
0x4E	III	bge disp9	if Greater than or equal; signed	[(S xor OV) = 0]
0x4F	III	bgt disp9	if Greater than - signed	[((S xor OV) or Z) = 0]


--Misc. 32-bit instructions---------------------
0x28	V	movea	imm16, reg1, reg2	Add; No flags	reg2 <-- reg1 + sign32(imm16)
0x29	V	addi	imm16, reg1, reg2	Add		reg2 <-- reg1 + sign32(imm16)
0x2A	IV	jr	disp26			Jump rel	PC <-- sign32(disp26) & 0xFFFF FFFE
0x2B	IV	jal	disp26			Jump and link	r31 <-- PC+4, jr disp26
0x2C	V	ori	imm16, reg1, reg2	Logical OR	reg2 <-- reg1 OR sign32(imm16)
0x2D	V	andi	imm16, reg1, reg2	Logical AND	reg2 <-- reg1 AND sign32(imm16)
0x2E	V	xori	imm16, reg1, reg2	Logical XOR	reg2 <-- reg1 XOR sign32(imm16)
0x2F	V	movhi	imm16, reg1, reg2	Add High	reg2 <-- reg1 + shl16(imm16)
0x30	VIa	ld.b	disp16[reg1], reg2	Load Byte	reg2 <-- [sign32(disp16) + reg1]
0x31	VIa	ld.h	disp16[reg1], reg2	Load HWord	reg2 <-- [sign32(disp16) + reg1]
0x32	UDEF					Undefined
0x33	VIa	ld.w	disp16[reg1], reg2	Load Word	reg2 <-- [sign32(disp16) + reg1]
0x34	VIb	st.b	reg2, disp16[reg1]	Store Byte	[sign32(disp16) + reg1] <-- reg2
0x35	VIb	st.h	reg2, disp16[reg1]	Store HWord	[sign32(disp16) + reg1] <-- reg2
0x36	UDEF					Undefined
0x37	VIb	st.w	reg2, disp16[reg1]	Store Word	[sign32(disp16) + reg1] <-- reg2
0x38	VIa	in.b	disp16[reg1], reg2	Inport Byte	reg2 <-- [sign32(disp16) + reg1]
0x39	VIa	in.h	disp16[reg1], reg2	Inport HWord	reg2 <-- [sign32(disp16) + reg1]
0x3A	VIa	caxi	disp16[reg1], reg2
0x3B	VIa	in.w	disp16[reg1], reg2	Inport Word		reg2 <-- [sign32(disp16) + reg1]
0x3C	VIb	out.b	reg2, disp16[reg1]	Outport Byte	[sign32(disp16) + reg1] <-- reg2
0x3D	VIb	out.h	reg2, disp16[reg1]	Outport HWord	[sign32(disp16) + reg1] <-- reg2
0x3E	VII	Floating Point Instructions	See sub-opcode table below
0x3F	VIb	out.w	reg2, disp16[reg1]	Outport Word	[sign32(disp16) + reg1] <-- reg2

All instructions greater than 0x3F are undefined.  Except for the Branch instructions which use a
7-bit opcode instead of a 6-bit opcode.

Unless otherwise noted, all mathematical operations are signed.


--BitString Sub-Opcodes------------------------
Sub-op	Inst		Summary
-------------------------------
0x00	sch0bsu		Search up, for 0's
0x01	sch0bsd		Search down, for 0's
0x02	sch1bsu		Search up, for 1's
0x03	sch1bsd		Search down, for 1's
0x04	UDEF		Undefined
0x05	UDEF		Undefined
0x06	UDEF		Undefined
0x07	UDEF		Undefined
0x08	orbsu		OR 2 BitStrings
0x09	andbsu		AND 2 BitStrings
0x0A	xorbsu		XOR 2 BitStrings
0x0B	movbsu		Store first BitString in second
0x0C	ornbsu		OR 2 BitStrings, NOT the first
0x0D	andnbsu		AND 2 BitStrings, NOT the first
0x0E	xornbsu		XOR 2 BitStrings, NOT the first
0x0F	notbsu		NOT first BitString, store in second
0x10	UDEF		Undefined
	.
	.
	.
0x1F	UDEF		Undefined


--Floating Point Sub-Opcodes--------------------
Sub-op	Syntax			Function		Operation
0x00	cmpf.s reg1, reg2	Compare FP		reg2 - reg1
0x01	UDEF			Undefined
0x02	cvt.ws reg1, reg2	Convert Int to Float	reg2 <-- float(reg1)
0x03	cvt.sw reg1, reg2	Convert Float to Int	reg2 <-- int(reg1)
0x04	addf.s reg1, reg2	Add			reg2 <-- reg2 + reg1
0x05	subf.s reg1, reg2	Subtract		reg2 <-- reg2 - reg1
0x06	mulf.s reg1, reg2	Multiply		reg2 <-- reg2 * reg1
0x07	divf.s reg1, reg2	Divide			reg2 <-- reg2 / reg1
0x08	UDEF			Undefined
0x09	UDEF			Undefined
0x0A	UDEF			Undefined
0x0B	trnc.sw reg1, reg2	Convert Float to UInt	reg2 <-- uint(reg1)
0x0C	UDEF			Undefined
	.
	.
	.
0x3F	UDEF			Undefined